The present invention relates in general to communication on a bus, and in particular to combining packets for transmission onto a bus that uses a packetized protocol.
Modern personal computer systems generally include a number of different devices, including processors, memory, data storage devices using magnetic or optical media, user input devices such as keyboards and mice, output devices such as monitors and printers, graphics accelerators, and so on. All of these devices communicate with each other via various buses implemented on a motherboard of the system. Numerous bus protocols are known, including PCI (Peripheral Component Interconnect), PCI-E (PCI Express), AGP (Advanced Graphics Processing), HyperTransport, and so on. Each bus protocol specifies the physical and electrical characteristics of the connections, as well as the format for transferring information via the bus. In many instances, the buses of a personal computer system are segmented, with different segments sometimes using different bus protocols, and the system includes bridge chips that interconnect different segments.
Typically, buses are used to exchange data between system components. For instance, when a graphics processor needs to read texture or vertex data stored in system memory, the graphics processor requests the data via a bus and receives a response via the same bus. Where many devices are making requests for data (e.g., from system memory) or where one device is making large or frequent requests, a bus or bus segment can become saturated, leading to decreased performance. In fact, many modern graphics processors are bandwidth-limited; that is, their performance is limited by the ability to deliver data via the bus that connects them to the rest of the system. Consequently, reducing traffic on the bus, which increases the available bandwidth, is expected to improve system performance. Techniques that reduce traffic on the bus would therefore be highly desirable.